Sciweavers

872 search results - page 114 / 175
» A Leakage-Resilient Mode of Operation
Sort
View
CGO
2010
IEEE
14 years 2 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
ICPPW
2008
IEEE
14 years 2 months ago
Energy Modeling of Processors in Wireless Sensor Networks Based on Petri Nets
Power minimization is a serious issue in wireless sensor networks to extend the lifetime and minimize costs. However, in order to gain an accurate understanding of issues regardin...
Ali Shareef, Yifeng Zhu
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
14 years 2 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
VR
2007
IEEE
160views Virtual Reality» more  VR 2007»
14 years 2 months ago
Dynallax: Solid State Dynamic Parallax Barrier Autostereoscopic VR Display
A novel barrier strip autostereoscopic (AS) display is demonstrated using a solid-state dynamic parallax barrier. A dynamic barrier mitigates restrictions inherent in static barri...
Tom Peterka, Robert Kooima, Javier Girado, Jinghua...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen