872 search results - page 13 / 175 » A Leakage-Resilient Mode of Operation |
ASYNC
2002
IEEE
14 years 14 days ago
2002
IEEE
For application in a software defined radio a CORDIC processor has been developed that can operate both in synchronous and asynchronous mode. Each mode of operation has advantages...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (Q...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
SIGSOFT
2001
ACM
14 years 8 months ago
2001
ACM
Layered architecture in operating system code is often compromised by execution path-specific customizations such as prefetching, page replacement and scheduling strategies. Paths...