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ISQED
2009
IEEE
112views Hardware» more  ISQED 2009»
14 years 2 months ago
Estimation and optimization of reliability of noisy digital circuits
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
Satish Sivaswamy, Kia Bazargan, Marc D. Riedel
ICCAD
1995
IEEE
114views Hardware» more  ICCAD 1995»
13 years 11 months ago
Sequential synthesis using S1S
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
LOPSTR
2009
Springer
14 years 2 months ago
The Dependency Triple Framework for Termination of Logic Programs
We show how to combine the two most powerful approaches for automated termination analysis of logic programs (LPs): the direct approach which operates directly on LPs and the trans...
Peter Schneider-Kamp, Jürgen Giesl, Manh Than...
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 11 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
ISQED
2009
IEEE
103views Hardware» more  ISQED 2009»
14 years 2 months ago
A systematic approach to modeling and analysis of transient faults in logic circuits
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
Natasa Miskov-Zivanov, Diana Marculescu