Sciweavers

1410 search results - page 132 / 282
» A Logic for Virtual Memory
Sort
View
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 9 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
119
Voted
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
15 years 9 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ARVLSI
1997
IEEE
105views VLSI» more  ARVLSI 1997»
15 years 8 months ago
An Embedded DRAM for CMOS ASICs
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
John Poulton
FPGA
2009
ACM
168views FPGA» more  FPGA 2009»
15 years 2 months ago
Large-scale wire-speed packet classification on FPGAs
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
Weirong Jiang, Viktor K. Prasanna
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
14 years 8 months ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...