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ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
16 years 1 months ago
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Functional decomposition is a fundamental operation in logic synthesis. Prior BDD-based approaches to functional decomposition suffer from the memory explosion problem and do not...
Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee
INFOCOM
2009
IEEE
15 years 11 months ago
Minimizing Rulesets for TCAM Implementation
—Packet classification is a function increasingly used in a number of networking appliances and applications. Typically, sists of a set of abstract classifications, and a set o...
Rick McGeer, Praveen Yalagandula
IPPS
2009
IEEE
15 years 11 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...
IWMM
2009
Springer
122views Hardware» more  IWMM 2009»
15 years 10 months ago
Parametric heap usage analysis for functional programs
This paper presents an analysis that derives a formula describing the worst-case live heap space usage of programs in a functional language with automated memory management (garba...
Leena Unnikrishnan, Scott D. Stoller
ASPDAC
2009
ACM
212views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Kwangok Jeong, Andrew B. Kahng