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» A Logical Account of NGSCB
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MEMOCODE
2003
IEEE
14 years 22 days ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
TLDI
2003
ACM
135views Formal Methods» more  TLDI 2003»
14 years 21 days ago
Typed compilation of recursive datatypes
Standard ML employs an opaque (or generative) semantics of datatypes, in which every datatype declaration produces a new type that is different from any other type, including othe...
Joseph Vanderwaart, Derek Dreyer, Leaf Petersen, K...
ICNP
2002
IEEE
14 years 12 days ago
Service Overlay Networks: SLAs, QoS and Bandwidth Provisioning
We advocate the notion of service overlay network (SON) as an effective means to address some of the issues, in particular, end-to-end QoS, plaguing the current Internet, and to f...
Zhenhai Duan, Zhi-Li Zhang, Yiwei Thomas Hou
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
13 years 11 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
DAC
1994
ACM
13 years 11 months ago
Exact Minimum Cycle Times for Finite State Machines
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
William K. C. Lam, Robert K. Brayton, Alberto L. S...