Sciweavers

1604 search results - page 174 / 321
» A Logical Viewpoint on Architectures
Sort
View
ISMVL
2005
IEEE
108views Hardware» more  ISMVL 2005»
14 years 4 months ago
Approaching the Physical Limits of Computing
As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. H...
Michael P. Frank
ICTAC
2005
Springer
14 years 4 months ago
Stochastic Analysis of Graph Transformation Systems: A Case Study in P2P Networks
In distributed and mobile systems with volatile bandwidth and fragile connectivity, non-functional aspects like performance and reliability become more and more important. To forma...
Reiko Heckel
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 3 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
DAC
1999
ACM
14 years 3 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
DAC
1997
ACM
14 years 2 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm