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» A Low Power Approach to Floating Point Adder Design
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ARITH
2009
IEEE
15 years 8 months ago
A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targe...
Claude-Pierre Jeannerod, Herve Knochel, Christophe...
WOTUG
2008
15 years 5 months ago
FPGA based Control of a Production Cell System
Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan I...
Marcel A. Groothuis, Jasper J. P. van Zuijlen, Jan...
PACS
2000
Springer
99views Hardware» more  PACS 2000»
15 years 7 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar
DAC
2007
ACM
16 years 5 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 9 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...