Sciweavers

154 search results - page 23 / 31
» A Low Power Highly Associative Cache for Embedded Systems
Sort
View
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
14 years 3 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...
INFOCOM
1998
IEEE
14 years 24 days ago
Adaptive Resource Management for Flow-Based IP/ATM Hybrid Switching Systems
This paper addresses a fundamental problem in resource management for flow-based hybrid switching systems. Such systems aim at efficient transport of layer-3 connectionless IP traf...
Hao Che, San-qi Li, Arthur Y. M. Lin
DAC
2006
ACM
14 years 9 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
RTAS
1996
IEEE
14 years 21 days ago
Supporting the specification and analysis of timing constraints
Real-time programmers have to deal with the problem of relating timing constraints associated with source code to sequences of machine instructions. This paper describes an enviro...
Lo Ko, Christopher A. Healy, Emily Ratliff, Robert...
CAL
2008
13 years 8 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny