Sciweavers

60 search results - page 6 / 12
» A Low-Energy FPGA: Architecture Design and Software-Supporte...
Sort
View
ERSA
2010
186views Hardware» more  ERSA 2010»
13 years 5 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
14 years 4 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
DAC
2006
ACM
14 years 8 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
13 years 11 months ago
A reconfigurable hardware based embedded scheduler for buffered crossbar switches
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassil...
ANCS
2008
ACM
13 years 9 months ago
Implementing an OpenFlow switch on the NetFPGA platform
We describe the implementation of an OpenFlow Switch on the NetFPGA platform. OpenFlow is a way to deploy experimental or new protocols in networks that carry production traffic. ...
Jad Naous, David Erickson, G. Adam Covington, Guid...