108 search results - page 14 / 22 » A Lower Bound for Dynamic Scheduling of Data Parallel Progra... |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
ICPP
1998
IEEE
13 years 11 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
DSD
2002
IEEE
14 years 13 days ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
POPL
2011
ACM
12 years 10 months ago
2011
ACM
A number of deterministic parallel programming models with strong safety guarantees are emerging, but similar support for nondeterministic algorithms, such as branch and bound sea...