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FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
14 years 1 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
GLVLSI
2006
IEEE
144views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Crosstalk analysis in nanometer technologies
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
Shahin Nazarian, Ali Iranli, Massoud Pedram
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
14 years 1 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
VLSI
2010
Springer
13 years 6 months ago
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
Eliyah Kilada, Shomit Das, Kenneth S. Stevens
BROADNETS
2005
IEEE
14 years 1 months ago
Measuring performance impact of security protocols in wireless local area networks
- In this paper, we study and quantify the impact of the most widely used security protocols, such as 802.1x, EAP, IPSEC, SSL and RADIUS, in wireless local area networks (WLANs). B...
Avesh Kumar Agarwal, Wenye Wang