Variation-aware routing for FPGAs

Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to FPGAs and ASICs to get a measure of the severity of the problem in both the FPGA and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95% for the same yield for the MCNC benchmarks. Categories and Subject Descriptors B.7 [Hardware]: Integrated Circuits; B.8 [Hardware]: Performance and Reliability General Terms Algorithms, Design, Performance, Experimentation Keywords Statistical Timing Analysis, FPGA Routing

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Satish Sivaswamy, Kia Bazargan
• Keywords: FPGA, FPGA 2007, Hardware, Process Variations, Statistical Optimization Techniques