98 search results - page 1 / 20 » A Memory Design in QCAs using the SQUARES Formalism |
GLVLSI
1999
IEEE
14 years 3 months ago
1999
IEEE
We present a formalism for implementing circuits with Quantum-dot Cellular Automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism s...
ISQED
2010
IEEE
14 years 26 days ago
2010
IEEE
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
ISLPED
1997
ACM
14 years 3 months ago
1997
ACM
Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data ...
DAC
1996
ACM
14 years 3 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...