179 search results - page 25 / 36 » A Memory Management System Optimized for BDMPI's Memory and ... |
ASPDAC
1998
ACM
14 years 1 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
IANDC
2006
13 years 8 months ago
2006
Abstract. History independent data structures, presented by Micciancio, are data structures that possess a strong security property: even if an intruder manages to get a copy of th...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
CGF
2010
13 years 9 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...