179 search results - page 25 / 36 » A Memory Management System Optimized for BDMPI's Memory and ... |
173
click to vote
ASPDAC
1998
ACM
15 years 10 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
171
click to vote
CODES
2008
IEEE
16 years 15 days ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
157
click to vote
IANDC
2006
15 years 6 months ago
2006
Abstract. History independent data structures, presented by Micciancio, are data structures that possess a strong security property: even if an intruder manages to get a copy of th...
175
click to vote
IEEEPACT
2005
IEEE
15 years 11 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
156
click to vote
CGF
2010
15 years 6 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...