Sciweavers

383 search results - page 19 / 77
» A Methodology for High Level Power Estimation and Exploratio...
Sort
View
RTCSA
2007
IEEE
14 years 2 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
VLSI
2012
Springer
12 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
RSP
2005
IEEE
207views Control Systems» more  RSP 2005»
14 years 1 months ago
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design
Embedded signal processing systems are usually associated with real-time constraints and/or high data rates so that fully software implementation are often not satisfactory. In th...
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
CE
2008
86views more  CE 2008»
13 years 7 months ago
Exploring the information literacy competence standards for elementary and high school teachers
The main purpose of this study was to establish Information Literacy Competence Standards for Elementary and High School Teachers. To establish these standards a set of two expert...
Jia-Rong Wen, Wen-Ling Shih
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 8 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...