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» A Methodology for High Level Power Estimation and Exploratio...
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EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 11 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
14 years 1 months ago
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Paul Zuber, Armin Windschiegl, Raúl Medina ...
ISSS
1995
IEEE
121views Hardware» more  ISSS 1995»
13 years 11 months ago
A comprehensive estimation technique for high-level synthesis
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...
Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min X...
ADHOCNOW
2006
Springer
14 years 1 months ago
Power-Aware Rate Control for Mobile Multimedia Communications
Consumers increasingly demand high quality of service (QoS) for multimedia applications. Rate control scheme is one of the major methods that provide high video quality for mobile ...
Hye-Soo Kim, Dinh Duong, Jae-Yun Jeong, Byoung-Kyu...
IPPS
2003
IEEE
14 years 1 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...