- This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a ded...
Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea ...
Recent developments in reconfigurable hardware technologies have offered high-density high-speed devices with the ability for custom computing whilst maintaining the flexibility o...
Next generation embedded systems place new demands on an efficient methodology for their design and verification. These systems have to support interaction over a network, multipl...
Josef Fleischmann, Klaus Buchenrieder, Rainer Kres...
Communications infrastructure for modular reconfiguration of FPGAs needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overhead...
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...