1609 search results - page 235 / 322 » A Microeconomic Scheduler for Parallel Computers |
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
HPCA
2007
IEEE
14 years 9 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper describes the dynamic load-balancing and high performance communication provided in Jcluster, an efficient Java parallel environment. For the efficient loadbalancing,...
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...