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MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
14 years 4 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 4 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 4 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
RTSS
2003
IEEE
14 years 4 months ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
COMPGEOM
2003
ACM
14 years 4 months ago
The smallest enclosing ball of balls: combinatorial structure and algorithms
We develop algorithms for computing the smallest enclosing ball of a set of n balls in d-dimensional space. Unlike previous methods, we explicitly address small cases (n ≤ d + 1...
Kaspar Fischer, Bernd Gärtner
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