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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 8 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
VTC
2008
IEEE
124views Communications» more  VTC 2008»
14 years 1 months ago
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien