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IEEEPACT
2006
IEEE
14 years 3 months ago
Complexity-based program phase analysis and classification
Modeling and analysis of program behavior are at the foundation of computer system design and optimization. As computer systems become more adaptive, their efficiency increasingly...
Chang-Burm Cho, Tao Li
IISWC
2006
IEEE
14 years 3 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 3 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
DATE
2005
IEEE
136views Hardware» more  DATE 2005»
14 years 3 months ago
Increasing Register File Immunity to Transient Errors
Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches an...
Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk
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