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114
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SAMOS
2004
Springer
15 years 8 months ago
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which s...
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Ra...
148
Voted
EMSOFT
2007
Springer
15 years 9 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...
171
Voted
EUROPAR
2009
Springer
15 years 6 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
138
Voted
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
15 years 7 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
131
Voted
IJCNN
2000
IEEE
15 years 7 months ago
Input Window Size and Neural Network Predictors
Neural Network approaches to time series prediction are briefly discussed, and the need to specify an appropriately sized input window identified. Relevant theoretical results fro...
Ray J. Frank, Neil Davey, S. P. Hunt