Sciweavers

982 search results - page 19 / 197
» A Multiprocessor Communication Architecture For High Speed N...
Sort
View
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 1 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
INFOCOM
2006
IEEE
14 years 1 months ago
JetMax: Scalable Max-Min Congestion Control for High-Speed Heterogeneous Networks
Recent surge of interest towards congestion control that relies on single-link feedback (e.g., XCP, RCP, MaxNet, EMKC, VCP), suggests that such systems may offer certain benefit...
Yueping Zhang, Derek Leonard, Dmitri Loguinov
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 5 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
DSN
2007
IEEE
14 years 1 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
VECPAR
2004
Springer
14 years 22 days ago
Message Strip-Mining Heuristics for High Speed Networks
In this work we investigate how the compiler technique of message strip mining performs in practice on contemporary high performance networks. Message strip mining attempts to redu...
Costin Iancu, Parry Husbands, Wei Chen