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ICCAD
1998
IEEE
98views Hardware» more  ICCAD 1998»
15 years 8 months ago
Determination of worst-case aggressor alignment for delay calculation
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...
CHI
1998
ACM
15 years 8 months ago
Exploring Browser Design Trade-Offs Using a Dynamical Model of Optimal Information Foraging
Designers and researchers of human-computer interaction need tools that permit the rapid exploration and management of hypotheses about complex interactions of designs, task condi...
Peter Pirolli
DATE
1997
IEEE
74views Hardware» more  DATE 1997»
15 years 8 months ago
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
This paper describes a practical test approach for analog-to-digital converters (ADCs) based on the oscillation-test strategy. The oscillation-test is applied to convert the ADC u...
Karim Arabi, Bozena Kaminska
PDP
1997
IEEE
15 years 8 months ago
The controlled logical clock--a global time for trace-based software monitoring of parallel applications in workstation clusters
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
Rolf Rabenseifner
ADL
1997
Springer
125views Digital Library» more  ADL 1997»
15 years 8 months ago
Error Tolerant Document Structure Analysis
Successful applications of digital libraries require structured access to sources of information. This paper presents an approach to extract the logical structure of text document...
Bertin Klein, Peter Fankhauser