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» A Network Memory Architecture Model and Performance Analysis
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137
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IPPS
2010
IEEE
15 years 1 months ago
Dynamic analysis of the relay cache-coherence protocol for distributed transactional memory
Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory (TM) promises to alle...
Bo Zhang, Binoy Ravindran
136
Voted
SC
2003
ACM
15 years 9 months ago
Job Superscheduler Architecture and Performance in Computational Grid Environments
Computational grids hold great promise in utilizing geographically separated heterogeneous resources to solve large-scale complex scientific problems. However, a number of major ...
Hongzhang Shan, Leonid Oliker, Rupak Biswas
127
Voted
JSA
2000
116views more  JSA 2000»
15 years 3 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
137
Voted
SECON
2008
IEEE
15 years 10 months ago
Content Distribution in VANETs Using Network Coding: The Effect of Disk I/O and Processing O/H
Abstract—Besides safe navigation (e.g., warning of approaching vehicles), car to car communications will enable a host of new applications, ranging from office-on-the-wheel supp...
Seung-Hoon Lee, Uichin Lee, Kang-Won Lee, Mario Ge...
155
Voted
ISCAPDCS
2007
15 years 5 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi