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» A Network Memory Architecture Model and Performance Analysis
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134
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ISPASS
2006
IEEE
15 years 9 months ago
Critical path analysis of the TRIPS architecture
Fast, accurate, and effective performance analysis is essential for the design of modern processor architectures and improving application performance. Recent trends toward highly...
Ramadass Nagarajan, Xia Chen, Robert G. McDonald, ...
119
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WSC
2000
15 years 5 months ago
Simulation as educational support for production and logistics in industrial engineering
The proposed implementation is a monitor system able to train operators for on-line real time manufacturing control in order to analyze the performance of a production process. Th...
Agostino G. Bruzzone, Pietro Giribone, Roberto Rev...
116
Voted
ACSAC
2008
IEEE
15 years 10 months ago
Defending Against Attacks on Main Memory Persistence
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
William Enck, Kevin R. B. Butler, Thomas Richardso...
125
Voted
CASES
2003
ACM
15 years 9 months ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara
116
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APLAS
2008
ACM
15 years 5 months ago
Certified Reasoning in Memory Hierarchies
Abstract. Parallel programming is rapidly gaining importance as a vector to develop high performance applications that exploit the improved capabilities of modern computer architec...
Gilles Barthe, César Kunz, Jorge Luis Sacch...