3629 search results - page 170 / 726 » A Network Memory Architecture Model and Performance Analysis |
161
Voted
APCSAC
2000
IEEE
15 years 7 months ago
2000
IEEE
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...
143
Voted
ISCAS
2005
IEEE
15 years 9 months ago
2005
IEEE
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
137
Voted
ICPP
2008
IEEE
15 years 10 months ago
2008
IEEE
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
139
Voted
CODES
2001
IEEE
15 years 7 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
169
Voted
CASES
2006
ACM
15 years 9 months ago
2006
ACM
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...