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» A Network Memory Architecture Model and Performance Analysis
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131
Voted
DAC
2006
ACM
16 years 4 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
146
Voted
IPPS
2005
IEEE
15 years 9 months ago
Enhancing NIC Performance for MPI using Processing-in-Memory
Processing-in-Memory (PIM) technology encompasses a range of research leveraging a tight coupling of memory and processing. The most unique features of the technology are extremel...
Arun Rodrigues, Richard C. Murphy, Ron Brightwell,...
152
Voted
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 10 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
132
Voted
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 7 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
158
Voted
WOSP
2005
ACM
15 years 9 months ago
Performance evaluation of UML software architectures with multiclass Queueing Network models
Software performance based on performance models can be applied at early phases of the software development cycle to characterize the quantitative behavior of software systems. We...
Simonetta Balsamo, Moreno Marzolla