3629 search results - page 43 / 726 » A Network Memory Architecture Model and Performance Analysis |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
ICPPW
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an analysis on the performance of a parallel implementation of a discrete model of laser dynamics, which is based on cellular automata. The performance of a 2D...
ICPPW
2002
IEEE
14 years 20 days ago
2002
IEEE
This paper reports our experiences on the Scalable Network Of Workstation (SNOW) project, which implements a novel methodology to support user-level process migration for traditio...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical...
IEEEHPCS
2010
13 years 6 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...