3629 search results - page 54 / 726 » A Network Memory Architecture Model and Performance Analysis |
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
HPCC
2005
Springer
14 years 1 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
ICDCS
1995
IEEE
13 years 11 months ago
1995
IEEE
One of the mostsoughtaftersoftware innovation of thisdecade is the construction of systems using off-the-shelf workstations that actually deliver, and even surpass, the power and ...
ICS
1999
Tsinghua U.
14 years 1 days ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
MSWIM
2009
ACM
14 years 2 months ago
2009
ACM
Fairness in multihop ad hoc networks has received considerable attention in the literature. Many schemes have been proposed, which attempt to compute the “optimal” bit rates o...