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» A Network Memory Architecture Model and Performance Analysis
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OTM
2009
Springer
14 years 3 months ago
Parallel Interconnection of Broadcast Systems with Multiple FIFO Channels
This paper proposes new protocols for the interconnection of FIFO- and causal-ordered broadcast systems, thus increasing their scalability. They use several interconnection links b...
Rubén de Juan-Marín, Vicent Cholvi, ...
CASES
2007
ACM
14 years 1 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
WMPI
2004
ACM
14 years 2 months ago
The Opie compiler from row-major source to Morton-ordered matrices
The Opie Project aims to develop a compiler to transform C codes written for row-major matrix representation into equivalent codes for Morton-order matrix representation, and to a...
Steven T. Gabriel, David S. Wise
ISPAN
1999
IEEE
14 years 1 months ago
Location Updates and Probabilistic Tracking Algorithms for Mobile Cellular Networks
In this work, we develop a novel mathematical model to analyze di erent location update protocols for mobile cellular network. Our model can capture many important features of use...
John C. S. Lui, Cedric C. F. Fong, H. W. Chan
ICONIP
1998
13 years 10 months ago
Computing Iterative Roots with Neural Networks
Many real processes are composed of a n-fold repetition of some simpler process. If the whole process can be modelled with a neural network, we present a method to derive a model ...
Lars Kindermann