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» A Network Memory Architecture Model and Performance Analysis
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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 2 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
JPDC
2010
137views more  JPDC 2010»
13 years 6 months ago
Parallel exact inference on the Cell Broadband Engine processor
—We present the design and implementation of a parallel exact inference algorithm on the Cell Broadband Engine (Cell BE). Exact inference is a key problem in exploring probabilis...
Yinglong Xia, Viktor K. Prasanna
GECCO
2003
Springer
142views Optimization» more  GECCO 2003»
14 years 1 months ago
Revisiting Elitism in Ant Colony Optimization
Ant Colony Optimization (ACO) has been applied successfully in solving the Traveling Salesman Problem. Marco Dorigo et al. used Ant System (AS) to explore the Symmetric Traveling S...
Tony White, Simon Kaegi, Terri Oda
HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
SIGMETRICS
2009
ACM
149views Hardware» more  SIGMETRICS 2009»
14 years 2 months ago
On the treeness of internet latency and bandwidth
Existing empirical studies of Internet structure and path properties indicate that the Internet is tree-like. This work quantifies the degree to which at least two important Inte...
Venugopalan Ramasubramanian, Dahlia Malkhi, Fabian...