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» A Network Memory Architecture Model and Performance Analysis
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RTSS
2006
IEEE
14 years 1 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
DAC
2005
ACM
14 years 8 months ago
MiniBit: bit-width optimization via affine arithmetic
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the intege...
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayn...
VLSISP
2010
119views more  VLSISP 2010»
13 years 2 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton
ROBIO
2006
IEEE
181views Robotics» more  ROBIO 2006»
14 years 1 months ago
3D Grasp Synthesis Based on Object Exploration
— Many approaches to robotic grasping have focused on a specific aspect of the problem only, without considering its integrability with other related procedures in order to buil...
Eris Chinellato, Gabriel Recatalá, Angel P....
VLDB
1998
ACM
138views Database» more  VLDB 1998»
14 years 2 days ago
TOPAZ: a Cost-Based, Rule-Driven, Multi-Phase Parallelizer
Currently the key problems of query optimization are extensibility imposed by object-relational technology, as well as query complexity caused by forthcoming applications, such as...
Clara Nippl, Bernhard Mitschang