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» A Network Memory Architecture Model and Performance Analysis
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2008
IEEE
14 years 2 months ago
High message rate, NIC-based atomics: Design and performance considerations
—Remote atomic memory operations are critical for achieving high-performance synchronization in tightly-coupled systems. Previous approaches to implementing atomic memory operati...
Keith D. Underwood, Michael Levenhagen, K. Scott H...
LCN
2008
IEEE
14 years 2 months ago
Understanding and using mobility on Publish/Subscribe based architectures for MANETs
Abstract—Mobile Ad Hoc Networks present several new challenges, mainly due to mobility. Publish/Subscribe is a communication paradigm that fits this network model well since the...
Cristiano G. Rezende, Azzedine Boukerche, Bruno P....
APCSAC
2007
IEEE
14 years 2 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 1 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
ISCAS
2005
IEEE
97views Hardware» more  ISCAS 2005»
14 years 1 months ago
Two-level decoupled Hamming network for associative memory under noisy environment
— Compared with a single level Hamming associative memory, a simple model based on uniform random noise analysis has proved a twolevel decoupled Hamming network to be an efficie...
Liang Chen, Naoyuki Tokuda, Akira Nagai