Sciweavers

50808 search results - page 318 / 10162
» A New
Sort
View
IPPS
2007
IEEE
14 years 5 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
IPPS
2007
IEEE
14 years 5 months ago
ParalleX: A Study of A New Parallel Computation Model
This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and th...
Guang R. Gao, Thomas L. Sterling, Rick Stevens, Ma...
IROS
2007
IEEE
109views Robotics» more  IROS 2007»
14 years 5 months ago
A new approach to segmentation of 2D range scans into linear regions
— Toward obtaining a compact and multiresolution representation of 2D range scans, a wavelet framework is proposed for encoding an orientation measure called Running Angle (RA). ...
Ahad Harati, Roland Siegwart
ISQED
2007
IEEE
156views Hardware» more  ISQED 2007»
14 years 5 months ago
A New Method of Implementing Hierarchical OPC
For emerging deep-subwavelength lithography technologies (90 nm and following) the data volume and the complexity of Optical Proximity Correction (OPC) have increased dramatically...
Yufu Zhang, Zheng Shi
MEMOCODE
2007
IEEE
14 years 5 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...
« Prev « First page 318 / 10162 Last » Next »