The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and th...
Guang R. Gao, Thomas L. Sterling, Rick Stevens, Ma...
— Toward obtaining a compact and multiresolution representation of 2D range scans, a wavelet framework is proposed for encoding an orientation measure called Running Angle (RA). ...
For emerging deep-subwavelength lithography technologies (90 nm and following) the data volume and the complexity of Optical Proximity Correction (OPC) have increased dramatically...
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...