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IEEEPACT
2002
IEEE
14 years 14 days ago
Effective Compilation Support for Variable Instruction Set Architecture
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
Jack Liu, Timothy Kong, Fred C. Chow
PROCEDIA
2011
12 years 10 months ago
A Multilevel Parallelism Support for Multi-Physics Coupling
A new challenge in scientific computing is to merge existing simulation models to create new higher fidelity combined (often multi-level) models. While this challenge has been a...
Fang Liu, Masha Sosonkina
ASPLOS
2009
ACM
14 years 8 months ago
Kendo: efficient deterministic multithreading in software
Although chip-multiprocessors have become the industry standard, developing parallel applications that target them remains a daunting task. Non-determinism, inherent in threaded a...
Marek Olszewski, Jason Ansel, Saman P. Amarasinghe
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
14 years 25 days ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
IPPS
2009
IEEE
14 years 2 months ago
Dynamic parallelization for RNA structure comparison
In this paper we describe the parallelization of a dynamic programming algorithm used to find common RNA secondary structures including pseudoknots and similar structures. The se...
Eric Snow, Eric Aubanel, Patricia Evans