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ISCAS
2002
IEEE
82views Hardware» more  ISCAS 2002»
15 years 9 months ago
Logic synthesis for PLA with 2-input logic elements
In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA with 2-input logic elements can achieve low-power dissipation and high-speed oper...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...
IFIP
1999
Springer
15 years 8 months ago
A Synthesis Algorithm for Modular Design of Pipelined Circuits
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
Maria-Cristina V. Marinescu, Martin C. Rinard
LCN
1996
IEEE
15 years 8 months ago
A Class-Chest for Deriving Transport Protocols
Development of new transport protocols or protocol algorithms suffers from the complexity of the envir onment in which they ar e intended to run. Modeling techniques attempt to av...
W. Timothy Strayer
TIP
2010
277views more  TIP 2010»
14 years 11 months ago
Distance Regularized Level Set Evolution and Its Application to Image Segmentation
Level set methods have been widely used in image processing and computer vision. In conventional level set formulations, the level set function typically develops irregularities du...
Chunming Li, Chenyang Xu, Changfeng Gui, Martin D....
CCGRID
2011
IEEE
14 years 8 months ago
High Performance Pipelined Process Migration with RDMA
—Coordinated Checkpoint/Restart (C/R) is a widely deployed strategy to achieve fault-tolerance. However, C/R by itself is not capable enough to meet the demands of upcoming exasc...
Xiangyong Ouyang, Raghunath Rajachandrasekar, Xavi...