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    » A New Method for Design of Robust Digital Circuits
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    ICCD
    2006
    IEEE
    183views Hardware» more  ICCD 2006»
    An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
    14 years 6 months ago
    An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
    Download  iccd.et.tudelft.nl
    The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs. In this paper, ...
    Sanjay Pant, David Blaauw
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    DOCENG
    2007
    ACM
    109views Document Analysis» more  DOCENG 2007»
    Preserving the aesthetics during non-fixed aspect ratio scaling of the digital border
    14 years 1 months ago
    Preserving the aesthetics during non-fixed aspect ratio scaling of the digital border
    Download  www2.engr.arizona.edu
    To enhance the visual effect of a photo, various digital borders or frames are provided for photo decoration at photo sharing websites. Even though multiple versions of the same b...
    Hui Chao, Prasad Gabbur, Anthony Wiley
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    DAC
    1995
    ACM
    111views Computer Architecture» more  DAC 1995»
    Hierarchical Optimization of Asynchronous Circuits
    14 years 19 days ago
    Hierarchical Optimization of Asynchronous Circuits
    Download  cwc.ucsd.edu
    Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
    Bill Lin, Gjalt G. de Jong, Tilman Kolks
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    CIKM
    2004
    Springer
    134views Information Technology» more  CIKM 2004»
    The robustness of content-based search in hierarchical peer to peer networks
    14 years 2 months ago
    The robustness of content-based search in hierarchical peer to peer networks
    Download  www.cs.cmu.edu
    Hierarchical peer to peer networks with multiple directory services are an important architecture for large-scale file sharing due to their effectiveness and efficiency. Recent ...
    M. Elena Renda, Jamie Callan
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    ISCAS
    2006
    IEEE
    86views Hardware» more  ISCAS 2006»
    Fast timing analysis of plane circuits via two-layer CNN-based modeling
    14 years 3 months ago
    Fast timing analysis of plane circuits via two-layer CNN-based modeling
    Download  nlab.ee.tokushima-u.ac.jp
    Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
    Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifum...
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