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» A New Method for Design of Robust Digital Circuits
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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
14 years 1 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
IJRR
2007
117views more  IJRR 2007»
13 years 9 months ago
Wave Haptics: Building Stiff Controllers from the Natural Motor Dynamics
— Haptics, like the fields of robotics and motion control, relies on high stiffness position control of electric motors. Traditionally DC motors are driven by current amplifier...
Nicola Diolaiti, Günter Niemeyer, Neal A. Tan...
GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
13 years 11 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
14 years 2 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
DAC
1997
ACM
14 years 1 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...