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» A New Method for Design of Robust Digital Circuits
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FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
14 years 1 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
14 years 3 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
14 years 2 months ago
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim...
GECCO
2005
Springer
190views Optimization» more  GECCO 2005»
14 years 2 months ago
An efficient evolutionary algorithm applied to the design of two-dimensional IIR filters
This paper presents an efficient technique of designing twodimensional IIR digital filters using a new algorithm involving the tightly coupled synergism of particle swarm optimiza...
Swagatam Das, Amit Konar, Uday Kumar Chakraborty
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 2 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee