509 search results - page 52 / 102 » A New Multiport Memory for High Performance Parallel Process... |
DAGSTUHL
2008
13 years 10 months ago
2008
Existing selfverifying solvers for dense linear (interval-)systems in C-XSC provide high accuracy, but are rather slow. A new set of solvers is presented, which are a lot faster th...
HPCA
1998
IEEE
14 years 1 months ago
1998
IEEE
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
The trend of increasing speed and complexity in the single-core processor as stated in the Moore’s law is facing practical challenges. As a result, the multi-core processor arch...
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...