509 search results - page 58 / 102 » A New Multiport Memory for High Performance Parallel Process... |
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
The Cray MTA-2 system provides exceptional performance on a variety of sparse graph algorithms. Unfortunately, it was an extremely expensive platform. Cray is preparing an Eldorad...
JPDC
2006
13 years 8 months ago
2006
We describe a new suite of computational benchmarks that models applications featuring multiple levels of parallelism. Such parallelism is often available in realistic flow comput...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
IJPP
2002
13 years 8 months ago
2002
This paper presents a compilation framework that allows executable code to be shared across different Java Virtual Machine (JVM) instances. All fully compliant JVMs that target se...