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IPPS
1994
IEEE
14 years 1 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ICDCS
2002
IEEE
14 years 1 months ago
Fast Collect in the absence of contention
We present a generic module, called Fast Collect. Fast Collect is an implementation of Single-Writer Multi-Reader (SWMR) Shared-Memory in an asynchronous system in which a process...
Burkhard Englert, Eli Gafni
SPAA
1999
ACM
14 years 1 months ago
Recursive Array Layouts and Fast Parallel Matrix Multiplication
Matrix multiplication is an important kernel in linear algebra algorithms, and the performance of both serial and parallel implementations is highly dependent on the memory system...
Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K....
IPPS
1996
IEEE
14 years 1 months ago
Implementing the Data Diffusion Machine Using Crossbar Routers
The Data Diffusion Machine is a scalable virtual shared memory architecture. A hierarchical network is used to ensure that all data can be located in a time bounded by O(logp), wh...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
CODES
2004
IEEE
14 years 18 days ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis