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ICPPW
2009
IEEE
14 years 3 months ago
Multiprocessor Synchronization and Hierarchical Scheduling
Multi-core architectures have received significant interest as thermal and power consumption problems limit further increase of speed in single-cores. In the multi-core research ...
Farhang Nemati, Moris Behnam, Thomas Nolte
HPCA
2012
IEEE
12 years 4 months ago
System-level implications of disaggregated memory
Recent research on memory disaggregation introduces a new architectural building block—the memory blade—as a cost-effective approach for memory capacity expansion and sharing ...
Kevin T. Lim, Yoshio Turner, Jose Renato Santos, A...
SIGCOMM
2009
ACM
14 years 3 months ago
Crossbow: a vertically integrated QoS stack
This paper describes a new architecture which addresses Quality of Service (QoS) by creating unique flows for applications, services, or subnets. A flow is a dedicated and indep...
Sunay Tripathi, Nicolas Droux, Thirumalai Srinivas...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 10 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
MMS
2008
13 years 8 months ago
Evalvid-RA: trace driven simulation of rate adaptive MPEG-4 VBR video
Due to the increasing deployment of conversational real-time applications like VoIP and videoconferencing, the Internet is today facing new challenges. Low end-to-end delay is a vi...
Arne Lie, Jirka Klaue