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» A New Statistical Optimization Algorithm for Gate Sizing
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SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
14 years 1 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 4 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
ICCAD
2003
IEEE
138views Hardware» more  ICCAD 2003»
14 years 4 months ago
Multi-Million Gate FPGA Physical Design Challenges
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Maogang Wang, Abhishek Ranjan, Salil Raje
CIBCB
2007
IEEE
13 years 9 months ago
Optimization of Bacterial Strains with Variable-Sized Evolutionary Algorithms
—In metabolic engineering it is difficult to identify which set of genetic manipulations will result in a microbial strain that achieves a desired production goal, due to the co...
Miguel Rocha, José P. Pinto, Isabel Rocha, ...
DAC
2009
ACM
14 years 11 days ago
GPU-based parallelization for fast circuit optimization
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
Yifang Liu, Jiang Hu