Total leakage power optimization with improved mixed gates

Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness of gate oxide layer Tox. In this paper, we propose a new method that combines approaches of Dual Threshold CMOS (DTCMOS), mixed-Tox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits – design aids General Terms Algorithms, Performance Keywords Leakage currents, threshold voltage, MVT

• Type: Conference
• Year: 2005
• Where: SBCCI
• Authors: Frank Sill, Frank Grassert, Dirk Timmermann
• Keywords: Gate Oxide, SBCCI 2005, Threshold Voltage, Threshold Voltage Vth