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» A New Statistical Optimization Algorithm for Gate Sizing
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ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 4 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 4 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
14 years 1 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
DC
2010
13 years 7 months ago
Distributed algorithms for ultrasparse spanners and linear size skeletons
We present efficient algorithms for computing very sparse low distortion spanners in distributed networks and prove some non-trivial lower bounds on the tradeoff between time, spar...
Seth Pettie
ESA
2004
Springer
151views Algorithms» more  ESA 2004»
13 years 11 months ago
On Variable-Sized Multidimensional Packing
The main contribution of this paper is an optimal bounded space online algorithm for variable-sized multidimensional packing. In this problem, hyperboxes must be packed in ddimens...
Leah Epstein, Rob van Stee