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» A Note on Designing Logical Circuits Using SAT
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DAC
2008
ACM
14 years 8 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
CF
2008
ACM
13 years 9 months ago
Exact combinational logic synthesis and non-standard circuit design
Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first ba...
Paul Tarau, Brenda Luderman
GECCO
2005
Springer
128views Optimization» more  GECCO 2005»
14 years 25 days ago
Fractional dynamic fitness functions for GA-based circuit design
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
Cecília Reis, José António Te...
ISVLSI
2005
IEEE
124views VLSI» more  ISVLSI 2005»
14 years 27 days ago
Boost Logic: A High Speed Energy Recovery Circuit Family
In this paper, we propose Boost Logic, a logic family which relies on voltage scaling, gate overdrive and energy recovery techniques to achieve high energy efficiency at frequenc...
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad ...
ISMVL
2010
IEEE
209views Hardware» more  ISMVL 2010»
14 years 12 days ago
Secure Design Flow for Asynchronous Multi-valued Logic Circuits
—The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques ...
Ashur Rafiev, Julian P. Murphy, Alexandre Yakovlev