522 search results - page 18 / 105 » A Note on Designing Logical Circuits Using SAT |
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
CAV
2009
Springer
14 years 7 months ago
2009
Springer
We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, enc...
GECCO
2009
Springer
13 years 12 months ago
2009
Springer
A non-uniform cellular automata-based model is presented for the evolutionary development of digital circuits at the gate level. The main feature of this model is the modified lo...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Carbon Nanotube Field-Effect Transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits o...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...